Dr.Rajesh Saha

Information

  • Designation : Assistant Professor
  • Email : rajesh@ece.nits.ac.in
  • Phone : 9957880236

Key Notes

  • Conference: International - 14
  • Journals: 102
  • Conferences: 17
  • Book Chapters: 6
  • Books: 2
  • Patents: 2
  • PhD: Guided: 5
  • Post Graduates: Guided: 11
  • Under Graduates: Guided: 6

127

PUBLICATIONS

5

DOCTORAL STUDENTS

2

PATENTS

1

PROJECT

Introduction [Biosketch]

  • Rajesh Saha Assistant Professor in the Department of Electronics and Communication Engineering, National Institute of Technology Silchar. Before joining NIT Silchar, he has worked as Assistant Professor at MNIT Jaipur from February 2020 to November 2023 and School of Electronics Engineering, VIT AP University, from May 2018 to February 2020. He has received B.E. with honours in Electronics and Telecommunication Engineering from Assam Engineering College, Guwahati, Assam in 2012 and M. Tech. in Mobile Communication and Computing from NIT Arunachal Pradesh, Yupia, in 2015. He has received Ph.D. in Electronics and Communication from NIT Silchar, Assam in 2018. His research interest includes Modeling and Simulation of Nanoelectronics Devices, Biosensors.

Institution Year Degree
NIT Silchar 2018 PhD
NIT ARunachal Pradesh 2015 M Tech
Assam Engineering College 2012 B E

Teaching Experience
Assistant Professor
21 November 2023 - 21 March 2025
NIT Silchar

Assistant Professor
27 February 2020 - 20 November 2023
MNIT Jaipur

Assistant Professor
9 May 2018 - 26 February 2020
VIT AP University

Industrial/Research Experience
Research Asoociate
5 March 2020 - 30 April 2020
NIT SIlchar

Lakshmi Nivas Teja, Rashi Chaudhary, Shreyas Tiwari, Rajesh Saha, “Elimination of the Impact of Trap Charges through Heterodielectric BOX in Nanoribbon FET”, Nanoelectronic Devices and Applications, 2025, ISBN: 9789815238259, Benthma Scienc, Indexed in Scopus

Rupam Goswami and Rajesh Saha., “Contemporary Trends in Semiconductor Devices: Theory, Experiment and Applications”, 2022, Springer

B. Bhowmick, R. Goswami, and R. Saha, “Simulation and Modelling of Emerging Devices: Tunnel FET and FINFET”, 2023, Cambridge Scholars Publishing, 2023, Lady Stephenson Library, Newcastle upon Tyne, United Kingdom

Sl.No Course Name Semester Course Code Duration Status
1 Control System B.Tech EC 206 AY 2023-2024 Completed
2 Basic Electronics B.Tech EC 101 AY 2023-2024 Completed
3 Analog Electronics B.Tech EC 202 AY 2024-2025 Completed
4 Basic Electronics B.Tech EC 101 AY 2024-2025 Completed
5 VLSI Design B.Tech EC 309 AY 2024-2025 Completed
6 Simulation of Device and Circuit B.Tech EC 333 AY 2024-2025 Completed

Home Automation

Raj Verma and Vikash
Completed
Supervisor : Rajesh Saha
Academic Year : 2024-2025

TFET

Aman Singh and Priyambada Hazarika
Completed
Supervisor : Rajesh Saha
Academic Year : 2024-2025

Santhosh Andra and Chinni Saiteja
Supervisor : Rajesh Saha
Academic Year : 2023-2024

TFET

Yakshraj Sharma, Lakshya Vijay, Archita Kumari, Muskan
Completed
Supervisor : Rajesh Saha
Academic Year : 2022-2023

TFET

Tarun Kumar Bhardwaj, Vaibhav Jain, Sagar Bharti, Shubhankar Shyamal
Completed
Supervisor : Rajesh Saha
Academic Year : 2021-2022

Third Eye for the Blind

Ayush Mangla, Mohit Soni, Vedashree Bhide, Akhila Oruganti
Completed
Supervisor : Rajesh Saha

TFET

Jatismar Saha
Completed
Supervisor : Rajesh Saha
Academic Year : 2024-2025

TFET

Shiva Kumar
Completed
Co Supervisor : Rajesh Saha
Academic Year : 2023-2024

NRFET

Shasank Rai
Completed
Co Supervisor : Rajesh Saha
Academic Year : 2023-2024

NRFET

S L Nivas Teja
Completed
Supervisor : Rajesh Saha
Academic Year : 2022-2023

TFET

Khan Abdulkarim Abdulquyyaum
Completed
Supervisor : Rajesh Saha
Academic Year : 2022-2023

TFET

Lobzang Chonzom
Completed
Supervisor : Rajesh Saha
Academic Year : 2022-2023

VLSI Design

Mrigendra Singh
Completed
Supervisor : Rajesh Saha
Academic Year : 2021-2022

TFET

Gara Srinivasar
Completed
Supervisor : Rajesh Saha
Academic Year : 2021-2022

TFET

JITENDRA KUMAR
Completed
Supervisor : Rajesh Saha
Academic Year : 2021-2022

TFET

Harsh Nagendra
Co Supervisor : Rajesh Saha

CNT FET

Krishna Pal
Completed
Supervisor : Rajesh Saha

Angothu Saida
Ongoing
Supervisor : Rajesh Saha
Co Supervisor : Dipjyoti Das
Academic Year : 2025-2026

TFET

Shreyas Tiwari
Supervisor : Rajesh Saha
Academic Year : 2024-2025

FinFET

Ravindra Kr Maurya
Completed :  4 November 2024
Supervisor : Brinda Bhowmick
Co Supervisor : Rajesh Saha
Academic Year : 2024-2025

FinFET

Rashi Chaudhary
Completed :  6 December 2024
Supervisor : Rajesh Saha
Academic Year : 2024-2025

NSFET

Manosh Protim Gogoi
Ongoing
Supervisor : S Baishya
Co Supervisor : Rajesh Saha

Awards And Honours

    • Enlisted in top 2% Scientist in the world list for given by Stanford University and Elsevier Year – 2024
    • Enlisted in top 2% Scientist in the world list for given by Stanford University and Elsevier Year – 2023
    • Received IEI Young Engineers Award 2022-23, given by The Institution of Engineers (India) Year – 2022
    • Best Paper Award for for Paper Presentation given by 4th Int. Conference DevIC 2021 Year – 2021
    • Best Session Paper Award for Paper presented at Micro 2020 given by 7th International Conference on Microelectronics, Circuits and Systems 2020 (Micro 2020), Year – 2020
    • Received B. E. with honors from Assam Engineering College
    • Secured 10th rank in “Mathematical Talent Search Examination” held on 2004
    • Recipient of Anundoram Borooah award in 2005

A System for Developing and Analyzing a Parameter of Bohm Quantum Potential

“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”

German
Patent Registration ID, 202022105580
A System for Developing and Analyzing a Parameter of Bohm Quantum Potential, (**GRANTED**)

PORTABLE SYSTEM FOR FAST DETECTION OF P, QRS AND T WAVE FROM ECG SIGNALS

“A SYSTEM FOR STUDYING AND PERFORMING THE PART-OF-SPEECH TAGGING FOR MIZO LANGUAGE”

India
Patent Registration ID, 201931027301
PORTABLE SYSTEM FOR FAST DETECTION OF P, QRS AND T WAVE FROM ECG SIGNALS, (**GRANTED**)

Sl.No: 1

Title Of Research Project: " Impact of Lateral Straggle on the Logic Gates, SRAM, and Ring Oscillator in Silicon on Insulator (SOI) Tunnel FET "

Sponsored By: SERB

Overall Budget: Rs 2308000

Duration: Dec 06, 2019 - Jun 06, 2022 (2 years 6 months)

Status: Completed

Principal Investigator: Dr. Rajesh Saha

Sl.No Award/Recognition/Achievement Year Approved agency
1 IEI Young Engineers Award 2022-23 2022 The Institution of Engineers (India)
2 Enlisted in top 2% Scientist in the world list 2023 Stanford University and Elsevier
3 Enlisted in top 2% Scientist in the world list 2024 Stanford University and Elsevier

Sl.No Course Title Resource Person Documents Area Funding Agency Date
1 Workshop on Emerging Cutting Edge Technologies in CMOS: Trends and Challenges IEEE EDS SB, NIT Silchar, India Dec 11 2024 - Dec 15 2024
2 Emerging Nanoscale Semiconductor Devices and Integration with Machine Learning Verification NIT Silchar Institute May 14 2025 - May 18 2025
3 MATLAB Programming India E&ICT Aug 22 2022 - Sep 02 2022
4 Research methodology and authoring/reviewing Manuscripts India E&ICT Jul 25 2022 - Aug 05 2022
5 Scientific Computation and GUI Development Using MATLAB India E&ICT Mar 21 2022 - Mar 31 2022
6 Emerging CMOS Technologies and Beyond: Trends and Challenges India TEQIP Nov 26 2020 - Nov 30 2020
7 AISP 2020 at VIT AP University, Amaravati, AP India Jan 10 2020 - Jan 12 2020
Important Notice